1. Field of the Invention
The present invention generally relates to a semiconductor device and a method of manufacturing the semiconductor device, and more particularly, to a semiconductor device for high-frequency amplification and a method of manufacturing the semiconductor device.
2. Description of the Related Art
Field-effect transistors have been known as semiconductor devices that are suitable for amplifications in high-frequency bands of microwaves, sub-millimeter waves, millimeter waves, and the likes. The factors that hinder high-frequency operations of those field-effect transistors include the source-drain parasitic capacitance and the drain-gate parasitic capacitance. To operate a field-effect transistor at a high speed, it is necessary to minimize those parasitic capacitances.
Japanese Unexamined Patent Publication No. 2003-297854 discloses a technique of forming a source wall that extends from the source electrode to a point between the gate electrode and the drain electrode through a region above the gate electrode. By this technique, the parasitic capacitance of a semiconductor device can be reduced.
By the technique (prior art) disclosed in Japanese Unexamined Patent Publication No. 2003-297854, the parasitic capacitance between the gate and the drain of a semiconductor device cannot be adequately reduced.